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S75WS-N Based MCPs
Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with 128 Mb (8M x 16-Bit) RAM Type 4 and 512 Mb (32M x 16-bit) Data Flash or 1 Gb ORNAND Flash
Data Sheet
PRELIMINARY
Notice to Readers: This document indicates states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that a product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication Number S75WS-N_02
Revision A
Amendment 2
Issue Date October 6, 2005
Preliminary
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
S75WS-N Based MCPs
Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with 128 Mb (8M x 16-Bit) RAM Type 4 and 512 Mb (32M x 16-bit) Data Flash or 1Gb ORNAND Flash
Data Sheet
PRELIMINARY
General Description
The S75WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: One or more S29WS-N code Flash RAM Type 4 One or more S29WS-N data Flash, or one or more S30MS-P ORNAND Flash The products covered by this document are listed in the table below:
Code Flash Density 256 Mb S75WS256NDF S75WS256NEG 128 Mb RAM Density 256 Mb NOR Data Flash Density 512 Mb ORNAND Data Flash Density 1024 Mb
Device
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V High Performance -- 54 MHz, 66 Mhz, 80 MHz Packages -- 9 x 12 mm 84 ball FBGA -- 11 x 13 mm 115 ball FBGA Operating Temperature -- Wireless, -25C to +85C
Publication Number S75WS-N_02
Revision A
Amendment 2
Issue Date October 6, 2005
Preliminary
Contents
S75WS-N Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1 2 3 4 5 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 NOR Flash + pSRAM + ORNAND Flash MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5.1 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Connection Diagram - NOR Flash & 1.8 V RAM Type 4 Based Pinout, 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Connection Diagram - ORNAND-Based Pinout, 11 x 13 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Physical Dimensions - FEA084 - Fine Pitch Ball Grid Array 9 x 12 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.5 Physical Dimensions - FND115 - Fine Pitch Ball Grid Array 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MCP Revisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2.1 Table 2.2 Table 3.1 Table 3.2 MCP Configurations and Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ORNAND Configurations and Valid Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 NOR Flash and RAM Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ORNAND Flash Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Tables
6
Figures
Figure 4.1 Figure 4.2 MCP Block Diagram 1 ......................................................................................................................... 6 ORNAND Block Diagram ...................................................................................................................... 7
2
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
Preliminary
1
Product Selector Guide
Device Model Numbers LK NK MCP Configuration Code Flash RAM (Mb) Code RAM Data Storage Density Density (Mb) (Mb) Flash DYB pSRAM Data Flash Flash pSRAM Power-Up (RAM Type 4) Density Speed Speed State Supplier (Mb) (MHz) (MHz) (See Note) 54 54 0 1 0 1 0 1 4 9x12 Package 84 ball FBGA (mm)
S75WS256NDF
LJ NJ LH NH
WS256N
128
2xWS256N
256
128
512
66
66
80
80
b
Note: 0 (Protected), 1 (Unprotected [Default State])
1.1
NOR Flash + pSRAM + ORNAND Flash MCPs
Device Model Numbers UK UJ NOR Flash Density ORNAND Flash Density pSRAM Density MCP Speed 54 MHz 66 MHz 512 Mb 1024 Mb 256 Mb 80 MHz 54 MHz 66 MHz 80 MHz 1.8 V pSRAM Type 4 x8 x16 11 x 13 x 1.4 mm Supplier ORNAND Bus Width Package
S75WS256NEG
UH SK SJ SH
October 6, 2005 S75WS-N_02_A2
S75WS-N Based MCPs
3
Preliminary
2
Ordering Information
The ordering part number is formed by a valid combination of the following: S75WS 256 N D F BA W L K0
Packing 0 = 2 = 3 = RAM K J H Type Tray 7" Tape and Reel 13" Tape and Reel
Supplier; Speed Combination = RAM Type 4, 54 MHz = RAM Type 4, 66 MHz = RAM Type 4, 80 MHz
Package Dimensions and Ball Count; DYB Power Up; Flash Device Family (Data Storage) L = 1.4 mm, 9 x 12, 84 ball; 0, WS as Data Flash N = 1.4 mm, 9 x 12, 84 ball; 1, WS as Data Flash U = 1.4mm, 11x13, 115-ball, x16 ORNAND Data Flash S = 1.4mm, 11x13, 115-ball, x8 ORNAND Data Flash Temperature Range W = Wireless (-25C to +85C) Package Type And Material BA = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Package Data Flash Density F = 512 Mb G = 1024 Mb RAM Density D = 128 Mb E = 256 Mb Process Technology N = 110 nm, Mirror Bit Technology Code Flash Density 256 = 256 Mb Device Family S75WS = Multi-chip Product (MCP) 1.8-volt Burst Mode Flash Memory, RAM, and data flash
Table 2.1
S75WS256N
MCP Configurations and Valid Combinations
D F Valid Combination BA, BF W L, N K, H
Table 2.2
S75WS256N
ORNAND Configurations and Valid Combinations
E G Valid Combination BA, BF W U, S K, J, H
Package Marking Note:
The BGA package marking omits the leading S75 and packing type designator from the ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
Preliminary
3
Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1
Symbol Amax - A0 DQ15 - DQ0 OE# WE# VSS NC RDY CLK Address Inputs
NOR Flash and RAM Input/Output Descriptions
Description
Data Inputs/Outputs Output Enable input Write Enable input Ground No Connect; not connected internally. Ready output. Indicates the status of the Burst read. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid input. Indicates to device that the valid address is present on the address inputs. Hardware reset input. Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for pSRAM Chip-enable input for Code Flash. Chip-enable input for Data Flash 1. Chip-enable input for Data Flash 2. Control Register Enable. Flash 1.8 Volt-only single power supply. pSRAM Power Supply. Upper Byte Control. Lower Byte Control . (pSRAM) (pSRAM - RAM Type 4 only) Asynchronous relative to CLK for Burst Mode. (Flash) (Flash) (Common) (Common)
AVD# F-RST# F-WP#
F-ACC
R-CE# F1-CE# F2-CE# F2-CE# R-MRS# F-VCC R-VCC R-UB# R-LB#
Table 3.2 identifies the ORNAND input and output connections provided on the device.
Table 3.2
Symbol N-PRE N-ALE N-CLE N-CE# N-WP# N-WE# N-RE# N-RY/BY# N-I/O0-N-I/O15 N-VCC
ORNAND Flash Input/Output Descriptions
Description
ORNAND Power-On Read Enable. Tie to VSS on customer board if not used. ORNAND Address Latch Enable ORNAND Command Latch Enable ORNAND Chip-enable ORNAND Write-protect ORNAND Write-enable ORNAND Read-enable ORNAND Ready-Busy--this is shared with NOR RDY ORNAND I/O signals (I/O0-I/O7 for x8 bus width) ORNAND Power supply
October 6, 2005 S75WS-N_02_A2
S75WS-N Based MCPs
5
Preliminary
4
MCP Block Diagram
A0-A22 A23 A0-A22 A23
RDY
RDY
DQ0-DQ15
DQ0-DQ15
CLK AVD# F1-CE# OE# F-RST# F-ACC F1-WP# F-WE#
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256N Flash Memory
VSS
VSS
VCC VCCQ
F-VCC F-VCCQ
A0-A22
WAIT#
DQ0-DQ15
R-CE#
CLK AVD# CE# OE# LB# UB# WE# MRS#
128Mb Memory
R-LB# R-UB# R-MRS#
VSS VCC VCCQ
R-VCC R-VCCQ
A0-A22 A23 RDY DQ0-DQ15
F2-CE#
FD-WP#
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256N Flash Memory
VSS VCC VCCQ
A0-A22 A23 RDY DQ0-DQ15
F3-CE# v
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256N Flash Memory
VSS VCC VCCQ
Notes:
1. 2. MRS is only present in RAM Type 4. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second and third Flash devices, respectively.
Figure 4.1
MCP Block Diagram 1
6
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
Preliminary
x16 MS01GP-based MCP
A0-A22 A23
A0-A22 A23
RDY CLK AVD# F-CE# OE# F-RST# F-ACC F1-WP# WE#
RDY
DQ0-DQ15
DQ0-DQ15
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256N Flash Memory
VSS
VSS
VCC VCCQ
F-VCC
A0-A22
WAIT#
DQ0-DQ15
R1-CE# R-LB# R-UB# R-MRS#
CLK AVD# CE# OE# LB# UB# WE# MRS#
128 Mb RAM Memory
VSS VCC VCCQ
R-VCC
A0-A22
WAIT#
DQ0-DQ15
R2-CE#
CLK AVD# CE# OE# LB# UB# WE# MRS#
128 Mb RAM Memory
VSS VCC VCCQ
I/O0-I/O15
I/O0-I/O15
N-RY/BY#
RB#
N-CLE N-CE# N-ALE N-RE# N-WP# N-WE#
CLE CE# ALE RE# WP# WE#
MS01GP x16 ORNAND Memory
VSS PRE
N-VSS N-PRE
VCC
N-VCC
Figure 4.2 ORNAND Block Diagram October 6, 2005 S75WS-N_02_A2 S75WS-N Based MCPs 7
Preliminary
5
5.1
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S75WS.
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
5.2
Connection Diagram - NOR Flash & 1.8 V RAM Type 4 Based Pinout, 9 x 12 mm
Legend:
A1
DNU
A10
DNU
X
RFU (Reserved for Future Use)
B2
ADV#
B3
VSS
B4
CLK
B5
RFU
B6
F-VCC
B7
RFU
B8
RFU
B9
RFU
C2
F1-WP#
C3
A7
C4
R-LB#
C5
F-ACC
C6
WE#
C7
A8
C8
A11
C9
F2-CE#
X
Data Flash Shared Only
D2
A3
D3
A6
D4
R-UB#
D5
F-RST#
D6
RFU
D7
A19
D8
A12
D9
A15
X
Flash 2 Data Only
E2
A2
E3
A5
E4
A18
E5
RDY
E6
A20
E7
A9
E8
A13
E9
A21
X
Flash 3 Data Only
F2
A1
F3
A4
F4
A17
F5
RFU
F6
A23
F7
A10
F8
A14
F9
A22
X
Flash 1 Code Only
G2
A0
G3
VSS
G4
DQ1
G5
RFU
G6
RFU
G7
DQ6
G8
RFU
G9
A16
X
RAM Only
H2
F1-CE#
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
R-MRS#
X
All Shared
J2
R-CE1#
J3
DQ0
J4
DQ10
J5
F-VCC
J6
R-VCC
J7
DQ12
J8
DQ7
J9
VSS
X
All Flash Shared Only
K2
RFU
K3
DQ8
K4
DQ2
K5
DQ11
K6
RFU
K7
DQ5
K8
DQ14
K9
FD-WP#
X
Do Not Use
L2
RFU
L3
RFU
L4
VSS
L5
F-VCC
L6
F3-CE#
L7
RFU
L8
F-VCCQ
L9
DNU
M1
DNU
M10
DNU
8
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
Preliminary
5.3
Connection Diagram - ORNAND-Based Pinout, 11 x 13 mm
Legend
A1 DNU B1 DNU A2 DNU B2 DNU C2 AVD# D1 C3 VSS D3 A7 E3 A6 F3 A5 G3 A4 H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 RFU C4 CLK D4 R-LB# E4 R-UB# C5 RFU D5 F-ACC E5 F-RST# F5 RDY G5 RFU H5 RFU J5 DQ3 K5 F-VCC L5 DQ11 M5 F-VCC C6 IO15 D6 WE# E6 R2-CE# C7 IO14 D7 A8 E7 A19 F7 A9 G7 A10 H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 IO1 C8 IO13 D8 A11 E8 A12 F8 A13 G8 A14 H8 RFU J8 DQ15 K8 DQ7 L8 DQ14 M8 IO2 A9 DNU B9 DNU C9 IO12 A10 DNU B10 DNU Do Not Use C10 DNU NOR Flash Only D9 IO11 E9 A15 D10 IO10 E10 IO9 PSRAM 1 Only NAND Flash Only Reserved for Future Use
D2
N-RY/BY# F-WP# E1 N-RE# F1 N-CE# G1 N-VCC H1 N-VSS J1 N-CLE# K1 N-ALE# L1 N-WE# M1 DNU N1 DNU P1 DNU E2 A3
F2 A2
F4 A18 G4 A17 H4 DQ1
F6 A20 G6 A23 H6 RFU
F9 A21 G9 A22 H9 A16
F10 IO8 G10 N-VCC H10 N-VSS J10 IO7 K10 IO6 L10 IO5 M10 PRE N10 DNU
G2 A1 H2 A0
PSRAM 2 Only
PSRAM Shared Only
J2 F1-CE# K2 R1-CE# L2 N-WP# M2 RFU N2 DNU P2 DNU
J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS
J6 DQ4 K6 R-VCC L6 RFU M6 IO0
J9 R-MRS K9 VSS L9 IO4 M9 IO3 N9 DNU
NOR Flash & PSRAM Shared
P9 DNU
P10 DNU
Note: Bus 1: NOR Flash + pSRAM, Bus 2: ORNAND Flash
October 6, 2005 S75WS-N_02_A2
S75WS-N Based MCPs
9
Preliminary
5.4
Physical Dimensions - FEA084 - Fine Pitch Ball Grid Array 9 x 12 mm
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE
7
E eE
E1
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 FEA 084 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.10 1.11 NOM ------12.00 BSC. 9.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A2,A3,A4,A5,A6,A7,A8,A9 B1,B10,C1,C10,D1,D10 E1,E10,F1,F10,G1,G10 H1,H10,J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 0.45 MAX 1.40 --1.26 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
10
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005
Preliminary
5.5
Physical Dimensions - FND115 - Fine Pitch Ball Grid Array 11 x 13 mm
D
0.15 C (2X)
10 9 8 7 6 5 4 3 2 1
A
eD
D1
SE
7
E eE
E1
P
NM
LK
J
HGF
E
DCB
A
PIN A1 CORNER
9 INDEX MARK
B
7
PIN A1 CORNER
TOP VIEW A A2 A1
6
0.15 C (2X) 0.20 C
SD
BOTTOM VIEW
SIDE VIEW b
MCAB MC
C
0.08 C
115X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD SE 0.35 FND 115 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.17 0.98 NOM ------13.00 BSC. 11.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 115 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.40 --1.15 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9. 6 7 NOTE 4. 5. 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3524 \ 16-038.19 \ 10.5.05
A3-A8,B3-B8,C1,N3-N8,P3-P8 DEPOPULATED SOLDER BALLS
October 6, 2005 S75WS-N_02_A2
S75WS-N Based MCPs
11
Advance
Information
6
MCP Revisions
Revision A0 (February 17, 2005)
Initial Release
Revision A1 (September 8, 2005)
Global Removed references to the S29RS-N data sheet Product Selector Guide Updated table and added 80 MHz options Ordering Information Updated table with new options MCP Configurations and Valid Combinations Updated table to reflect new options Input/Output Descriptions Updated table and changed some pin names MCP Block Diagram Updated the illustration Connection Diagram Updated the pinout diagram Physical Dimensions Added the FEA084 package diagram Look-Ahead Connection Diagram Removed from data sheet S29WS-N Flash Module Updated to the latest revision
Revision A2 (October 6, 2005)
Global Added ORNAND Flash information Product Selector Guide Added ORNAND options Ordering Information Updated table with new options MCP Block Diagram Added the ORNAND illustration Connection Diagram Added the pinout diagram for the ORNAND device Physical Dimensions Added the FND115 package diagram
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S75WS-N Based MCPs
S75WS_02_A2 October 6, 2005
Advance
Information
S29WS-N Flash Module Removed from MCP. Available as a standalone document. 1.8 V Type 4 pSRAM Module Removed from MCP. Available as a standalone document.
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October 6, 2005 S75WS_02_A2
S75WS-N Based MCPs
13

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